“Facts are stubborn things” (John Adams, et al).

I added two 50-ohm outputs to the schematic of my published voltage-to-frequency converter (VFC) circuit (Figure 1). Then, I designed a PCB, purchased the (mostly) surface-mount components, loaded and re-flow soldered them onto the PCB, and then tested the design.

Figure 1 VFC design that operates from 100 kHz to beyond 100 MHz with a single 5.25-V supply, providing square wave outputs at 1/2 and 1/4 the main oscillator frequency.  

The hardware implementation of the circuit can be seen in Figure 2.

Figure 2  The hardware implementation of the 100MHz VFC was created in order to root out the facts that can only be obtained after it was built.

My objective was to get the facts about the operation of the circuit. 

Theory and simulation are important, but the facts are known only after the circuit is built and tested. That is when the unintended/unexpected consequences are seen.

The circuit mostly performed as expected, but there were some significant issues that had to be addressed in order to get the circuit performing well.

Sensitivity of the v-to-f

My first concern was the high sensitivity of the circuit to minute changes in the input voltage.  The sensitivity is 100 MHz per 5 volts, i.e., 20 MHz per volt. That means a 1-mV change on the input results in a 20-kHz change in the output frequency!

So, how do you supply an input voltage that is almost totally devoid of noise and/or ripple, which will cause jitter on the oscillator signal? To deal with this problem, I used a battery supply, four alkaline batteries in series, connected to a 10-turn, 100-kΩ potentiometer to drive the input of the circuit with about 0 to 6 V. This worked quite well. I added a 10 kΩ resistor in series with the non-inverting input of U1 for protection against overvoltage.

Problems and fixes

The first unexpected problem was that the NE555 timer did not provide sufficient drive to the voltage inverter circuit and the voltage doubler circuit. This one is on me; I didn’t look carefully at the datasheet, which says it can supply a lot of output current, but at high current, the output voltage drops so much that the inverter and the doubler circuits don’t provide enough output voltage. And the LTspice model I used for simulation was a very unrealistic model. I recommend that it not be used!

I fixed this by using a 74HC14 Schmitt trigger chip to replace the NE555 timer chip. The 74HC14 provides plenty of current and voltage to drive the two circuits. I implemented the 74HC14 circuitry as an outboard attachment to the main PCB. 

I changed the output of the voltage doubler circuit to a regulated 6 V (R16 changed to 274 Ω and R18 to 3.74 kΩ, and D8, D9 changed to SD103). This allows U1 to operate with an input voltage of up to about 5.9 V. Also, I substituted a TLV9162 dual op-amp for U1/U2 because the cost of the TLV9162 is much less than that of the LT1797. 

With the correct voltages supplied to U1/U2, I began testing the circuit, and I found that the oscillator would hang at a frequency of about 2 MHz. This was caused by the paralleled Schmitt trigger inverters. One inverter would switch before the other one, which would then sink the current from the inverter that had switched to the HIGH output state, and the oscillator would stop functioning. Paralleling inverters, which are driven by a relatively slowly falling (or rising) input signal, is definitely not a viable idea!

To fix the problem, I removed U4 from the circuit and put a 22-Ω resistor in series with the output of inverter U3 to lessen the current load on it, and the oscillator operated as expected.

I made some changes to the current-to-voltage converter circuit to provide more adjustment range and to use the optimum values for the 5-V supply. I changed R8 to 3.09 kΩ, potentiometer R9 to 1 kΩ, and R13 to 2.5 kΩ.

Adjustments

There are two adjustments provided: R9 is an adjustment for the current-to-voltage converter U2, and R11 is an offset current adjustment. 

I adjusted R9 to set the oscillator frequency to 100 MHz with the input voltage set to 5.00 V, and then adjusted R11 at 2 MHz.

The percent error of the circuit increases at the lower frequencies; possibly due to diode leakage currents, or nonlinear behavior of the frequency to voltage converter consisting of D2 – D4 and C8 – C11?

Test results

With the noted changes implemented, I began testing the VFC. The problem of jitter on the output signal was apparent, especially at the lower frequencies. 

I realized that ripple and noise on the 5-V supply would cause jitter on the output signal. As noted on the schematic, the oscillator frequency is a function of the supply voltage.

To avoid this problem, I once again opted to use batteries to provide the supply voltage. I used six alkaline batteries to supply about +9 V and regulated the voltage down to +5 V with an LM317T regulator and a few other components. 

This setup achieves about the minimum ripple and noise on the supply and the minimum oscillator jitter. The remaining possible sources of noise/jitter are the switching supplies for U1, the feedback voltage to U1, and the switching on and off of the counters and the inverters, which can cause noise on the +5-V supply.

The frequency versus input voltage plot is not as linear as expected, but it is pretty good over a wide range of input voltage from 50 mV to 5.00 V for a corresponding frequency range of 1.07 MHz to 103.0 MHz (Figure 3 and Figure 4). The percent error versus frequency is shown in Figure 5.

Figure 3 The frequency from 1.07 MHz to 103.0 MHz versus input voltage from 50 mV to 5.00 V.

Figure 4 The frequency (up to 2 MHz) versus input voltage when Vin < 0.1 V.

Figure 5 The percent error versus frequency.

Waveforms

Some waveforms are shown in Figure 6, Figure 7, Figure 8, and Figure 9. Most are from the divide-by-2 output because it is more visually interesting than the 3.4-ns output from the oscillator (multiply the divide-by-2 frequency by 2 to get the oscillator frequency). 

The input voltage ranges from 10 mV to 5 V to produce the 200 kHz to 100 MHz oscillator/inverter output.

Figure 6 Oscilloscope waveform with a divide-by-two output at 100 kHz.

Figure 7 Oscilloscope waveform with a divide-by-two output at 500 kHz.

Figure 8 Oscilloscope waveform with a divide-by-two output at 5 MHz.

Figure 9 Oscilloscope waveform with a divide-by-two output at 50 MHz.

Figure 10 displays the output of the oscillator/inverter at 100 MHz.  Figure 11 shows the 3.4 ns oscillator/inverter output pulse. 

Figure 10 Oscilloscope waveform with the oscillator output at 100 MHz.

Figure 11 Oscilloscope waveform with a 3.4-ns oscillator pulse.

The facts

So, here are the facts. 

The two inverters in parallel did not work in this application. This was fixed by eliminating one of them and putting a larger resistor in series with the output of the remaining one to reduce the current load on it.

The high sensitivity of the circuit to the input voltage presents a challenge in practice. Generating a sufficiently quiet input voltage is difficult.

Battery operation provides some help, but this presents its own challenges in practice. Noise on the 5-V supply is a related problem. The supply for the second divide-by-two circuit, U7, must be tightly regulated and extremely free of noise and ripple to minimize jitter on the oscillator signal.

And, as noted above, some changes in the values of several components were necessary to get acceptable operation.

Finally, more accurate voltage-versus-frequency operation at lower frequencies will require more careful engineering, if desired. I leave this to the user to work this out, if necessary. 

At this point, I am satisfied with the circuit as it is (I feel that it is time to take a break!).

Some suggestions for improved results

The circuit is compromised by the challenge to make it work with a single 5-V supply. It would be less challenging if separate, well-regulated, well-filtered supplies were used for U1/U2, for example, a 14 V regulated down to 11 V for the positive supply, and a negative 5 V regulated down to -2.5 V (use linear regulators for both supplies!) 

The input could then range from 0 to 10 V, which would reduce the input sensitivity by a factor of two and make it easier to design quieter supplies for the input amplifier and current-to-voltage circuits, U1/U2.

At the lower frequencies, some investigation should be done to expose the causes of the nonlinearity in that frequency range, and to indicate changes that would improve the circuit operation.

Another option would be to split the operation into two ranges, such as 100 kHz to 1 MHz and 1 MHz to 100 MHz.

Final fact

The operation of the circuit is pretty impressive when the circuit is modified as suggested. I think actualizing an oscillator that provides an output from 200 kHz to 113 MHz is quite a remarkable result. Thanks to the late Jim Williams [2] and to the lively Stephen Woodward [3] for leading the way to the implementation of this circuit!

Jim McLucas retired from Hewlett-Packard Company after 30 years working in production engineering and on the design and test of analog and digital circuits.

References/Related Content

1. A simulated 100-MHz VFC
2. 1-Hz to 100-MHz VFC features 160-dB dynamic range
3. 100-MHz VFC with TBH current pump
4. Take-Back-Half precision diode charge pump

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