Power Tips #129: Driving high voltage silicon FETs in 1000-V flybacks

The 800 V automotive systems enable higher performance electric vehicles capable of driving ranges longer than 400 miles on a single charge and charging times as fast as 20 minutes. 800 V batteries rarely operate at exactly 800 V and can go as high as 900 V with converter input requirements up to 1000 V.

There are a number of power design challenges for 1000-V-type applications, including field-effect transistors (FET) selection and the need to have a strong enough gate drive for >1,000 V silicon FETs which generally have larger gate capacitances than silicon carbide (SiC) FETs. SiC FETs have the advantage of lower total gate charge than silicon FETs with similar parameters; however, SiC often comes with increased cost.

You’ll find silicon FETs used in designs such as the Texas Instruments (TI) 350 V to 1,000 V DC Input, 56 W Flyback Isolated Power Supply Reference Design, which cascodes two 950 V FETs in a 54 W primary-side regulated (PSR) flyback. In lower-power general-purpose bias supplies (<10 W), it is possible to use a single 1,200 V silicon FET in TI’s Triple Output 10W PSR Flyback Reference Design which is the focus of this power tip.

This reference design can be a bias supply for the isolated gate drivers of traction inverters. It includes a wide input (60 V to 1000 V) PSR flyback with three isolated 33 V outputs, 100 mA loads, and uses TI’s UCC28730-Q1 as the controller. Figure 1 shows the UCC28730-Q1 datasheet with a 20-mA minimum drive current.

Figure 1 Gate-drive capability of the UCC28730-Q1 with a 20-mA minimum drive current. Source: Texas Instruments

The challenge is that the 1,200 V silicon FET will have a very large input capacitance (Ciss) of around 1,400 pF at 100 V VDS, which is 4 times more than a similarly rated SiC FET.

With a relatively weak gate drive from the UCC28730-Q1, Equation 1 estimates the primary FET turn-on time to be approximately 840 ns.

Figure 2 shows that as FET gate-to-source capacitance (C_GS) and gate-to-drain capacitance (C_GD) increases, it consumes the on-time of the primary FET required to regulate the output voltage of the converter.

Figure 2 FET turn on and off curves, as FET C_GS and C_GD increase, it consumes the on-time of the primary FET required to regulate the output voltage of the converter. Source: Texas Instruments

Figure 3 shows the undesirable effect of this by looking at the gate voltage of the UCC28730-Q1 driving the primary FET directly. In this example, it takes approximately 800 ns to completely turn on the FET and 1.5 µs for the gate to reach its nominal voltage. As you go to 400 V, the controller is still trying to charge C_GD when the controller decides to turn off the FET. It is much worse at 1,000 V where the C_GS is still being charged before turning off. This shows that as the input voltage increases, the controller cannot output a complete on-pulse and therefore the converter cannot power up to nominal output voltage.

Figure 3 Gate voltage of UCC28730-Q1 directly driving the primary FET with increasing input voltage. Source: Texas Instruments

To solve this, you can use a simple buffer circuit using two low-cost bipolar junction transistors as shown in Figure 4.

Figure 4 Simple N-Channel P-Channel N Channel-, P-Channel N-Channel P-Channel (NPN-PNP) emitter follower gate-drive circuit. Source: Texas Instruments

Figure 5 shows the gate current waveform of the primary FET and demonstrates the buffer circuit capable of gate drive currents greater than 500 mA.

Figure 5 Gate drive buffer current waveform of PMP23431, demonstrating that the buffer circuit is capable of gate drive current greater than 500 mA. Source: Texas Instruments

As shown in Equation 2, this reduces the charge time to 33 ns and is 25 times faster compared to just using the gate drive of the controller.

A PSR flyback architecture typically requires a minimum load current to stay within regulation. This helps increase the on-time and the converter can now power up to its minimum load requirements at 1000 V as shown in Figure 6. The converter’s overall performance is in the PMP23431 test report and Figure 7 shows the switching waveform with constant pulses on the primary FET. At 1,000 V with the minimum load requirement, the on-time is approximately 1 µs. Without this buffer circuit, the converter would not power up to 1,000 V input.

Figure 6 Converter startup with minimum load requirement with a 1000-V input. Source: Texas Instruments

Figure 7 Primary FET switching waveform of PMP23431 at 1000 V input. Source: Texas Instruments

In high voltage applications up to 1,000 V, the duty cycle can be quite small—in the hundreds of nanoseconds. A high-voltage silicon FET can be the limiting factor to achieving a well-regulated output due to its high gate capacitances. This power tip introduced PMP23431 and a simple buffer circuit to quickly charge the gate capacitances to support the lower on-times of these high voltage systems.

Darwin Fernandez is a systems manager in the Automotive Power Design Services team at Texas Instruments. He has been at TI for 14 years and has previously supported several power product lines as an applications engineer designing buck, flyback, and active clamp forward converters. He has a BSEE and MSEE from California Polytechnic State University, San Luis Obispo.

Related Content

• Power Tips #128: Designing a high voltage DC-link capacitor active precharge circuit
• Power Tips #76: Flyback converter design considerations
• Power Tips #98: Designing a DCM flyback converter
• Why use a BJT in a flyback converter?
• Power Tips #91: How to improve flyback efficiency with a nondissipative clamp
• Power Tips #77: Designing a CCM flyback converter
• Power Tips #17: Snubbing the flyback converter

Additional Resources

1. Read the application note, “Practical Considerations in High-Performance MOSFET, IGPT and MCT Gate-Drive Circuits.”
2. Check out the application report, “Fundamentals of MOSFET and IGBT Gate Driver Circuits.”
3. Download the PMP41009 reference design.

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