How to design a digital-controlled PFC, Part 3

Digital methods including oversampling, harmonic injection, and feedforward control reduce THD and improve power factor in PFC designs. The post How to design a digital-controlled PFC, Part 3 appeared first on EDN.

Electronics Apr 6, 2026 0 3 Add to Reading List

How to design a digital-controlled PFC, Part 3

Editor’s note: This is a multi-part series on how to design a digital-controlled PFC:

Total harmonic distortion (THD) and power factor are two major criteria used to evaluate power factor correction (PFC) performance. Meeting strict THD and power factor requirements is always a challenge for PFC designs. In this third installment of the series, I will introduce a set of digital methods to reduce THD and improve the power factor.

THD definition

THD is the total harmonic distortion present in a signal, defined as the ratio of the root-mean-square (RMS) amplitude of the total higher harmonic frequencies to the RMS amplitude of the fundamental frequency. Equation 1 expresses THD:

where Vn is the RMS value of the nth harmonic, and V1 is the RMS value of the fundamental component.

THD requirements have become stricter, especially in server applications, but meeting low THD requirements is more difficult than ever. The following methods can help reduce THD.

Make sure that the sensed signals are clean

To reduce THD, the first thing is to make sure that all of the sensed signals are clean. Because the sensed AC input voltage modulates the current reference, any spikes on the sensed AC signal will cause current reference distortion and affect THD.

One common practice is to put a decoupling capacitor close to the analog-to-digital converter (ADC) pin of the controller and set the resistor-capacitor filter cutoff frequency about 10 times higher than the frequency you are interested in. If the sensed AC voltage is still noisy, you can use a software phase-locked loop (SPLL) [1] to generate an internal sine-wave signal in phase with the AC voltage, and then use that generated sine-wave signal to modulate the current reference. Since the SPLL-generated sine wave is clean, even if there is some noise on the sensed AC voltage, the current loop reference will still be clean.

For VOUT sensing, you can use a digital infinite impulse response filter, as shown in Equation 2, to process the sensed VOUT to further reduce noise; because the PFC voltage loop is slow, the extra delay caused by this digital filter is acceptable.

where k<1.

Oversampling

The PFC inductor current has switching ripples. The current-sensing circuit may not provide sufficient attenuation to this current ripple. If you sample this signal only once in each switching period, there is no perfect, fixed location where the signal represents the average current all of the time. To get a more accurate feedback signal, consider using an oversampling mechanism.

Figure 1 shows an example that evenly samples the current feedback signal eight times in every switching cycle, averages the results, and sends them to the control loop. This oversampling effectively averages the current ripple out such that the measured current signal gets closer to the average current value. Also, the controller becomes less sensitive to noise.

Figure 1 Oversampling eight times in every switching cycle to average the current ripple out in order to allow the measured current signal to get closer to the average current value. (Source: Texas Instruments)

Reduce the current spikes at AC zero crossing

Current spikes at AC zero crossing are an inherent issue for totem-pole bridgeless PFC. These spikes can be so big that it becomes impossible to pass THD specifications. Reference [2] analyzes the root cause of these spikes and provides a PWM soft-start algorithm to effectively reduce them, as shown in Figure 2.

Figure 2 PWM soft start after AC zero crossing to prevent current spikes common to totem-pole brideless PFCs.(Source: Texas Instruments)

In this algorithm, when VAC changes from a negative to a positive cycle after AC zero crossing, boost switch Q2 turns on first with a very small pulse width, then gradually increases to the duty cycle (D) generated by the control loop. A soft start on Q2 gradually discharges the switch-node drain-to-source voltage (VDS) to zero. Once Q2 soft start is complete, synchronous transistor Q1 starts to turn on. It begins with a tiny pulse width and gradually increases until the pulse width reaches 1–D. When Q2 soft start is complete and Q1 soft start begins, the low-frequency switch Q4 turns on.

The transition from the AC positive cycle to the negative cycle is similar. Turning off all of the switches at the end of each half AC cycle leaves a small dead zone at AC zero crossing. Figure 3 shows the test result.

Figure 3 Current waveforms without and with a PWM soft start: the traditional control method (a); PWM soft start (b). (Source: Texas Instruments)

Reduce voltage-loop effects

The PFC output voltage has double-line frequency ripples. Although the voltage loop compensator can reduce these ripples, it cannot totally remove them; there are still some ripples coupled to the current reference that then affect THD.

One way to reduce the effect of these ripples is to add a digital notch (band-stop) filter between the VOUT sensed signal and the voltage loop. This notch filter can effectively attenuate the double-line frequency ripple while still passing all other frequency signals, including the sudden VOUT change caused by the transient load. The load transient response will not be affected.

Another approach is to use VOUT at the AC zero-crossing value, or VOUT_ZC(t), as a voltage feedback signal; see Figure 4. Since VOUT_ZC(t) equals the average value of VOUT, and since it is a “constant” in steady state, using it as feedback signal can eliminate the double-line frequency ripple.

Figure 4 VOUT at the AC zero-crossing instant, using this method can eliminate the double-line frequency ripple. (Source: Texas Instruments)

To handle the load transient, use the voltage loop control law shown in Figure 5.

Figure 5 Using VOUT_ZC(t) as a feedback signal in the steady state. (Source: Texas Instruments)

If the instantaneous error is small, use the value at the AC zero-crossing instance, which is VOUT_ZC, and a small Kp, Ki for the voltage loop compensator Gv. When a load transient occurs, causing an instantaneous VOUT error greater than the threshold, use the instantaneous VOUT value and a large Kp, Ki for Gv to rapidly bring VOUT back to its nominal value.

Duty-ratio feedforward control

As the name suggests, duty-ratio feedforward control precalculates a duty ratio, then adds this duty ratio to the feedback controller. For a boost topology operating in continuous conduction mode, Equation 3 gives the duty ratio feedforward (dFF) as:

Figure 6 depicts the resulting control scheme. After using Equation 3 to calculate dFF, add dFF to the traditional average current-mode control output (dI). Then use the final duty ratio (d) to generate a PWM waveform to control PFC.

Figure 6 Average current-mode control with dFF. (Source: Texas Instruments)

Since dFF generates the majority of the duty cycle, the control loop only adjusts the calculated duty slightly. This technique can help improve THD for applications with a limited controller loop bandwidth.

Harmonic injection

In cases where a specific order of harmonics is too high, and the methods I’ve described still cannot meet the THD specification, a harmonic injection method [3] may resolve the problem. The basic idea of this method is to generate a sinusoidal signal with the same order of the harmonic that you want to compensate, and inject this signal into the PFC current control loop to compensate for that harmonic.

There are two ways to generate a sinusoidal signal. The first method is to use an SPLL to track the AC voltage and then generate the corresponding high-order harmonics. The second method is to generate a sine-wave table and then read the table element at a different speed to obtain different orders of sine waves [3]. Figure 7 shows a test result on a PFC that initially has high third- and fifth-order harmonics.

Figure 7 Harmonic injection to reduce third- and fifth-order harmonics. (Source: Texas Instruments)

Power factor definition

The power factor is the ratio of real power in watts to apparent power, which is the product of the RMS current and RMS voltage in volt amperes, as shown in Equation 4:

Ideally, the power factor should be 1; the load will then appear as a resistor to the AC source. In the real world, however, electrical loads not only cause distortions in AC current waveforms but also make the AC current either lead or lag with respect to the AC voltage, resulting in a poor power factor. For this reason, Equation 5 calculates the power factor by multiplying the distortion power factor by the displacement power factor:

where φ is the phase angle between the current and voltage, and THD is the total harmonic distortion of the current.

Equation 5 also shows that to improve the power factor, the first thing to do is to reduce THD. However, low THD does not necessarily mean that the power factor is high. If the PFC AC input current and AC input voltage are not in phase, even if the current is a perfect sine wave (low THD), φ will result in a power factor less than 1.

The phase difference between the input current and input voltage is mainly caused by the electromagnetic interference (EMI) filter used in the PFC. Figure 8 shows a typical PFC circuit diagram that consists of three major parts: an EMI filter, a diode bridge rectifier, and a boost converter.

Figure 8 Circuit diagram of a typical PFC comprising an EMI filter, a diode bridge rectifier, and a boost converter. (Source: Texas Instruments)

In Figure 8, C1, C2, C3 and C4 are EMI X-capacitors. Simplifying Figure 8 results in Figure 9, where C is now a combination of C1, C2, C3, and C4.

Figure 9 Simplified EMI filter combining the capacitances shown in Figure 8. (Source: Texas Instruments)

The X-capacitor causes the AC input current to lead the AC voltage, as shown in Figure 10. The PFC inductor current is , the input voltage is , and the X-capacitor reactive current is . The total PFC input current is , which is also the current from where the power factor is measured. Although the PFC current control loop forces to follow , the reactive current of leads by 90 degrees, which causes to lead . The result is a poor power factor.

This effect is amplified at a light load and high line, as takes more weight in the total current. As a result, it is difficult for the power factor to meet a rigorous specification.

Figure 10 X-capacitor causes the AC current to lead the AC voltage. (Source: Texas Instruments)

Fortunately, with a digital controller, you can resolve this problem with one of the following methods.

Delay the current reference

Since makes the total current lead the input voltage, you can force to lag by some degree, as shown in Figure 11. The total current will then be in phase with the input voltage, improving the power factor.

Figure 11 Forcing to lag . (Source: Texas Instruments)

Since the current loop forces the inductor current to follow its reference, to let lag , the current reference needs to lag . To delay the current reference, a circulate buffer stores the measurement V_AC results. Then, instead of using the newest input voltage V_AC data, use previously stored V_AC data to calculate the current reference for the present moment. The current reference will lag ; the current loop will then make lag . This can compensate the leading X-capacitor and improve the power factor.

The delay period needs dynamic adjustment based on the input voltage and output load. The lower the input voltage and the heavier the load, the shorter the delay needed. Otherwise will be over delayed, making the power factor worse than if there were no delay at all. To resolve this problem, use a look-up table to precisely and dynamically adjust the delay time based on the operating condition.

Subtract from the current reference

Since a poor power factor is caused mainly by the EMI X-capacitor , if you calculate for a given X-capacitor value and input voltage and then subtract from the total ideal input current to form a new current reference for the PFC current loop, you will get a better total input current that is in phase with the input voltage and can achieve a good power factor.

To explain in more detail, for a PFC with a unity power factor of 1, is in phase with . Equation 6 expresses the input voltage:

where VAC is the AC input peak value, and f is the AC frequency. The ideal input current then needs to be totally in phase with the input voltage, expressed by Equation 7:

where IAC is the input current peak value.

Equation 8 expresses the capacitor current:

Equation 9 comes from Figure 9:

Combining Equation 7, Equation 8, and Equation 9 results in Equation 10:

If you use Equation 10 as the current reference for the PFC current loop, you can fully compensate the EMI X-capacitor , achieving a unity power factor. In Figure 12, the blue curve is the waveform of the preferred input current, i_AC(t), which is in phase with . The green curve is the capacitor current, i_C(t), which leads by 90 degrees. The red curve is i_AC(t) ‒ i_C(t). In theory, if the PFC current loop uses this red curve as its reference, you can fully compensate the EMI X-capacitor and increase the power factor.

Figure 12 New current reference. (Source: Texas Instruments)

Equation 10 requires a cosine waveform cos (2πƒt). To get this cosine waveform, use an SPLL to generate an internal sine wave synchronized with the input voltage. For microcontrollers that cannot perform trigonometric calculations, reference [4] describes another way to calculate iC(t).

Reduce THD and improve PF

If you need to reduce THD and improve the power factor, choose one or a combination of the methods discussed here. In the next installment of this series, I will talk about how to improve efficiency, limit re-rush current, implement e-metering, and reduce PFC bulk cap with a baby boost converter.

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References