A comparison of traditional and DSP-enabled ADCs in radio receivers

In a radio receiver, the analog-to-digital converter (ADC) sampling rate and the complexity of the analog anti-alias filter in front of it are not independent choices. A sampled system can uniquely represent signals only over a bandwidth of Fs/2, so any content falling outside the chosen Nyquist zone must be removed before it reaches the converter. The closer the sampling rate sits to the theoretical minimum, the narrower the filter’s transition band becomes, and the higher the filter order required to reach a given attenuation.

Sampling faster relaxes that filter. The reason designers do not simply sample much faster is the cost on the other side: a higher sampling rate means a more expensive converter and more data for the downstream FPGA or ASIC to process. The optimum sits wherever those two costs balance, and in a conventional signal chain, it’s the digital side that limits how far the balance can move.

That constraint changes when the converter itself performs the processing. ADCs are now available that integrate a DSP block alongside the ADC cores, providing decimation, digital downconversion (DDC), and IQ mismatch correction on chip.

Because the decimator reduces the output data rate, sampling faster no longer adds to the downstream burden; in fact, it can reduce it. The optimum moves toward higher sampling rates with relaxed analog filtering, and a significant portion of the digital front-end moves off the FPGA at the same time.

This article works through three radio receiver designs: a direct conversion receiver, a direct conversion receiver with digital channel selection, and an IF sampling receiver. These are each built around a 14-bit dual-channel ADC with an embedded DSP block from Silanna’s SD1148 family, which offers sample rates from 40 to 250 MS/s.

1. Direct conversion receiver

The direct conversion, or zero-IF, receiver architecture shown in Figure 1 uses a quadrature RF mixer that converts the RF signal directly to baseband. The signal chain starts with a band-select filter followed by a low noise amplifier (LNA), and the local oscillator (LO) is centered on the RF signal band.

Figure 1 Here is a simplified architecture of a direct conversion receiver. Source: Silanna

The mixer has two paths, one producing the in-phase (I) output and the other the quadrature (Q) output. So, a quadrature LO signal with sine and cosine components is required.

The baseband IQ signal path following the mixer typically consists of a programmable gain stage, an anti-alias filter, and finally the ADC. Many implementations include additional filtering along the signal chain and some amount of RF gain control. Channel selection can be either analog (by changing the LO frequency) or digital, in which case the LO frequency is fixed.

The entire band of interest is digitized by the ADC, and digital downconversion plus filtering are used to select the desired channel. Even with analog channel selection, channel-select filtering is often performed partially in the digital domain.

Implementation challenges

The direct conversion architecture does not have to deal with image rejection, as the signal is its own image. Its implementation challenges lie in LO feedthrough, 1/f noise, and gain transients. In the baseband, these issues are concentrated in the vicinity of DC and are most severe for systems using narrow channel widths, measured in kHz.

They are easier to deal with when using wider channel widths and modulations that are less sensitive to low-frequency content. When digital channel selection is used, placing the LO between channels largely solves them.

Another challenge is IQ mismatch: amplitude and phase mismatch between the I and Q components, which results in leakage between the I and Q signal paths. All baseband blocks, the mixer, and the LO contribute to this mismatch.

Differential gain errors between the I and Q paths in the mixer, amplifiers, and ADCs, together with the filter passband gain, contribute to gain mismatch. Phase mismatch is caused primarily by phase error between the LO sine and cosine components, by mismatch in the filter frequency response, and, to a lesser degree, by clock phase mismatch between the two ADCs.

Using dual devices for the amplifier and the ADC that are specifically designed for IQ applications significantly reduces the contribution from these blocks. Calibration is commonly required to suppress the remaining mismatch to a tolerable level. For signals with modest bandwidths, a frequency-independent calibration is typically sufficient.

Sampling rate and anti-alias filtering

ADC sampling-rate selection and baseband filtering are tightly coupled. Sampled systems, including ADCs, can uniquely represent signals only over a bandwidth of Fs/2, where Fs is the ADC sampling frequency. This condition is known as the Nyquist criterion.

If the ADC input contains spectral content in both the region from 0 to Fs/2 (the first Nyquist zone) and the region from Fs/2 to Fs (the second Nyquist zone), the sampling process folds frequency components from these regions onto one another. This effect is called aliasing and must be avoided. Either region can be used to place the signal of interest, but not both simultaneously.

The anti-alias filter is an analog filter placed in front of the ADC to suppress unwanted signal and noise content outside the selected Nyquist zone prior to sampling. When the signal band extends to Fs/2 − Δf, the frequencies that must be fully rejected by the filter begin at Fs/2 + Δf, giving a transition band 2Δf wide.

The narrower the transition band, the higher the filter order required to achieve a given attenuation. For this reason, it’s advantageous to increase the ADC sampling rate beyond the theoretical minimum stated by the Nyquist criterion in order to relax the filter specification. This margin is typically at least 30% and is often higher.

The trade-off is higher ADC cost and increased digital signal-processing requirements versus the cost and complexity of analog filtering. An ADC with an embedded DSP block offsets the digital processing burden, which shifts the optimum toward higher sampling rates with relaxed analog filtering.

Design example

The first example uses the dual ADC in a direct conversion receiver. The RF signal is a 26 MHz-wide band centered at 915 MHz. After downconversion, the baseband I and Q signals extend from 0 to 13 MHz. The ADC sampling rate is set to 65 MS/s, which provides a relaxed anti-alias filter transition band from 13 MHz to 52 MHz.

Figure 2 The above configuration represents a direct conversion receiver application. Source: Silanna

As shown in Figure 2, the DSP block offers adders and multipliers that can be programmed to correct the DC offset and the IQ gain mismatch. Hardware for IQ phase correction is also present. The user provides the control values for these blocks.

The DSP block includes a decimator that can be programmed for rates of two and four; in this case the rate is set to two. The decimation process includes a digital finite impulse response (FIR) low-pass filter whose passband is 40% of the output sampling rate, which here is 0.4 × 65 MHz/2 = 13 MHz, matching the requirement.

When a low-pass filter is applied to the I and Q paths separately, the combined effect produces a symmetric band-pass response centered at 0 Hz, resulting in a passband from −13 MHz to +13 MHz. Figure 3 shows the frequency-domain signals at each step of this direct conversion receive chain.

Figure 3 Here is how frequency domain signals look like in a direct conversion receiver. Source: Silanna

The decimator has reduced the output sampling rate to 32.5 MS/s. The combination of oversampling and digital filtering improves the signal-to-noise ratio by about 3 dB for every decimation factor of two.

One consequence is worth noting. Because the decimation filter suppresses signals in its stop band, it can affect the gain control loop of the system. If a strong signal is present at the ADC input, but is filtered out of the digital output, a loop that monitors the output might not detect that the ADC is starting to clip. This can be avoided by incorporating the overrange bit provided by the ADC into the gain control algorithm.

2. Direct conversion receiver with digital channel selection

The second example operates on the same 26 MHz RF band, now divided into four 6.5-MHz channels. The application receives one channel at a time, occasionally switching between channels.

Figure 4 The radio receiver design uses a built-in DDC to perform channel selection within the digitized band. Source: Silanna

The RF and analog portion of the receiver remains the same as in the first example. We enable the digital downconverter built into the ADC, shown in Figure 4, and tune the numerically controlled oscillator (NCO), which provides the digital LO to the center frequency of the desired channel. This shifts the selected channel to 0 Hz, as shown in Figure 5. The decimation factor can then be programmed to four, reducing the output sampling rate to 16.25 MS/s.

Figure 5 Frequency domain signals are shown in a direct conversion receiver using digital channel selection within the digitized band. Source: Silanna

We can also consider reducing the ADC sampling rate from 65 MS/s to the 50–55 MS/s range, which maintains reasonable anti-alias filter requirements while further reducing the output data rate. Using these DSP blocks offloads a significant amount of digital signal processing from the FPGA to the ADC, providing both cost and power savings.

3. IF sampling receiver

The third example uses an IF sampling radio architecture, which is essentially a superheterodyne receiver in which the second downconversion stage is implemented digitally. A simplified block diagram is shown in Figure 6. The RF signal is converted to baseband in two steps: first to an IF, where it is digitized, and then to baseband using a digital mixer.

Figure 6 IF sampling receiver converts RF signal to baseband in two steps. Source: Silanna

This architecture eliminates the IQ matching issues and the challenges in the vicinity of DC associated with direct conversion receivers. The improvement comes at a cost: the system must achieve image rejection, which typically requires more analog filtering.

In addition, the ADC input is at a higher frequency, which demands a higher-performance ADC and places tighter requirements on sampling-clock jitter. A common way to keep the ADC sampling rate reasonable is to locate the input signal in the second (or third) Nyquist zone. In the IF sampling receiver, the ADC input signal is real, requiring only a single ADC per receive chain instead of a dual-channel device.

Figure 7 IF sampling receiver is show with DSP’s DDC and decimation functions enabled. Source: Silanna

In this example, we process a 40 MHz RF signal in the 2.4 GHz ISM band. This requires an increased sampling rate than in previous examples, and the 210-MHz device from the same family was selected. The IF is chosen as 150 MHz, which places the image 300 MHz away from the desired signal at RF.

The ADC sampling rate is chosen as 200 MS/s, which centers the IF in the second Nyquist zone. Operating in higher Nyquist zones requires band-pass anti-alias filtering; in this case the lower stopband is from DC to 70 MHz, the passband is from 130 MHz to 170 MHz, and the upper stopband is from 230 MHz and above.

Figure 8 See the frequency domain signals in IF sampling receiver. Source: Silanna

The aliasing effect, which in this case is a useful feature of the sampling process, is used to bring the signal to a 50 MHz center frequency. It’s worth noting that a signal sampled from the second Nyquist zone appears spectrally inverted, so the alias that lands in the first Nyquist zone is flipped relative to the original. Figure 8 shows the spectrum of the signal throughout the signal chain.

Negative frequencies are typically omitted when dealing with real signals, as they are a mirror image of the positive frequencies. Here, however, it’s useful to note that the signal image in the negative frequencies is not flipped relative to the original analog signal. With this insight, we can enable the DDC and program the digital LO to −50 MHz. This rotates the spectrum by 50 MHz toward the positive frequencies, bringing the band to a 0-Hz center frequency with the proper orientation.

The image originally in the positive frequencies is now shifted toward Fs/2 and partially appears in the negative frequencies around −Fs/2. To remove this unwanted image and reduce excess bandwidth, the decimator must be enabled with a decimation factor of two or more. The 40-MHz signal bandwidth permits additional decimation, so the decimator is set to decimate-by-four.

This reduces the output sampling rate to 50 MS/s. Because we have translated a real signal into a complex one, we now have both I and Q components, which together carry the same data rate as a real 100 MS/s signal. The 40% decimator filter bandwidth results in a passband from −20 MHz to +20 MHz, a good fit for the 40-MHz signal band.

Common pattern in three RF architectures

The same pattern holds across all three architectures: moving decimation, digital downconversion, and IQ correction into the converter relaxes the analog filtering in front of it while reducing, rather than increasing, the data rate behind it.

In the direct conversion example, raising the sampling rate from 40 MS/s to 65 MS/s widened the anti-alias transition band by 2.8×, added 2.1 dB of oversampling gain, and still lowered the output data rate by 19%. In the channel-selection example, the output rate fell to 16.25 MS/s and the channel filter moved off the FPGA entirely. In the IF sampling example, a real 200-MS/s input became a complex 50 MS/s output with the unwanted image removed on chip.

The practical consequence is that the sampling-rate-versus-filter-order trade-off no longer must be settled in the analog domain alone. Where the digital front-end processing is effectively free, because it happens inside the converter, the optimum moves toward faster sampling and simpler analog filters, and a meaningful portion of the FPGA workload moves with it.

Mikko Waltari is director of data converter designs at Silanna.

Related Content

• Radio Architectures: ADCs and Receivers
• RF-sampling ADCs for multiband receivers
• A checklist for designing RF-sampling receivers
• Analyzing ADC Noise Impacts on Wireless System Performance
• ADC Parameters for Your Wideband Telecommunications Receiver

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