Rising respins and need for re-evaluation of chip design strategies

According to the wisdom of French philosopher Jean-Baptiste Alphonse Karr, “Plus ça change, plus c’est la même chose,” or “The more things change, the more they stay the same.” This adage holds significant relevance in the fast-paced world of the semiconductor industry. Currently, the industry is undergoing a profound technological shift fueled by diverse applications that mandate intricate custom chip designs.

Ground-breaking technologies such as artificial intelligence (AI), autonomous vehicles, edge processing and chiplets are triggering an avalanche of advancements in the semiconductor market. Pioneering technologies are paving the way for high-growth markets, maintaining a competitive edge for products and driving the demand for increasingly sophisticated systems-on-chips (SoCs) to power burgeoning applications.

As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.

The established hybrid design landscape

Over the past two decades, OEMs, Tier 1 suppliers and system designers have embraced a hybrid chip design model, predominantly operating independently. These companies frequently resort to customer-owned tooling (COT) for chip design, subsequently engaging with back-end services companies and wafer production management teams.

The COT model necessitates the recruitment of specialized semiconductor engineers from various disciplines for SoC development—a challenging feat due to the scarcity and steep cost of engineers. To address this need, companies often outsource talent to help manage temporary workload peaks and meet specific skillset demands. However, this workaround may not lead to forming a permanent, skilled team.

Large enterprises and startup companies alike must pay closer attention to the severe financial implications of design errors, which can sabotage budgets and delay market entry. In a recent study, a leading EDA firm reveals that over 60% of all first-time designs require a silicon re-spin. With millions of dollars of NRE on the line each time, plus the cost of delayed time to market, the rising complexity in chip design significantly amplifies the risk of errors, making any mistake potentially career-ending.

Figure 1 A 2020 functional verification study conducted by Siemens EDA and Wilson Research Group shows only 32% of 2020’s designs claimed first-silicon success.

Against this backdrop, the tech landscape continues to experience growth from venture capital-backed startups, particularly in the AI realm. These agile companies often utilize the COT model but face similar hurdles in designing distinctive, complex chips for their products. The technical expertise required to create sophisticated SoCs often exceeds their core competencies.

This underscores the need for experienced partners’ guidance throughout the chip design journey. Also, they frequently cannot source wafers directly from the industry’s leading foundry, TSMC, and instead are routed to a Value Chain Alliance (VCA) partner for mask creation and wafer production management.

These trends are driving a resurgence of ASIC design companies that now focus on “design and supply” services, offering a broad spectrum of technologies for customers to choose from. These firms possess the technical skills to guide customers in making informed selections of third-party IP and comprehend chiplet interconnect requirements, sophisticated SoC power management, 3D packaging, and more.

In short, this minimizes risk with new chip implementations and corresponding financial impacts. So, a new generation of ASIC companies with broad experience and stable engineering teams is emerging, capable of providing solid technology recommendations.

The imperative for a revamped model

Companies can preempt potential setbacks by collaborating with the new generation of ASIC design and supply firms that can manage the entire silicon development process. This necessity is spurring a re-evaluation of chip design strategies. The quest for unique differentiation and shorter development cycles is moving companies toward a collaborative relationship with their ASIC design partners.

This shift signals the demand for a new paradigm where companies are seeking alternatives capable of supporting the complete chip ecosystem, from inception to delivery. Adopting an integrated ASIC design and supply model offers significant advantages over traditional ASIC houses and reduces the investment associated with COT models.

An integrated ASIC design and supply model involves cross-functional teams collaborating closely with customers to define the entire semiconductor development and manufacturing process, including packaging, final testing and product lifecycle management.

Today’s SoCs are intricate, multi-billion-transistor devices custom-built for specific applications. The cost of developing such high-end chips can easily exceed $50 million, with the photomask set alone at advanced process nodes ranging from $10 million to $20 million. A collaboration with a technologically advanced, single-source ASIC design house can expedite chip development and help ensure first-time silicon success.

Figure 2 A single-source ASIC design house can expedite chip development and help ensure first-time silicon success. Source: Sondrel

Rich Wawrzyniak, principal analyst for The SHD Group, emphasizes the growing importance of ASIC-class services by stating, “In today’s complex technological landscape, ASIC-class services have become an essential part of the equation for handling advanced semiconductor design implementations.”

In the face of rapidly evolving technologies and the pressure to accelerate time to market, partnering with a single-source ASIC design and supply company appears increasingly beneficial. With its specialization in managing the entire chip development process, such a company can help chip designers architect their future and secure a competitive advantage.

Ian Walsh, Sondrel’s regional VP for America, is based in the company’s U.S. office in Santa Clara, California.

Related Content

• Nvidia Trains LLM on Chip Design
• AI-Powered Chip Design Goes Mainstream
• Creating a Center of Excellence for IC Design
• AI, and the Real Capacity Crisis in Chip Design
• It’s Just a Jump to the Left, Right? Shift Left in IC Design Enablement

The post Rising respins and need for re-evaluation of chip design strategies appeared first on EDN.