Powering AI at scale: How HVDC and GaN are transforming hyperscale data centers

As AI workloads and hyperscale data centers drive unprecedented power demand, operators face mounting pressure to improve efficiency and reduce grid strain. High-voltage direct current (HVDC) distribution is emerging as a critical solution, and GlobalFoundries is enabling this transition with advanced GaN technology that enables high-density, high-efficiency power conversion. This perspective explores how GF’s semiconductor innovations will power the next generation of sustainable, large-scale data centers.

The rapid adoption of AI across consumer and commercial markets is driving unprecedented investment in high-performance computing and networking. As AI models scale and proliferate across diverse applications, demand for compute power keeps rising. To meet this need, the power consumption of heterogeneous processing units (XPUs) is projected to climb from today’s 1–1.5 kW to more than 5 kW by 2030 [1]. This surge in power requirements is driving demand for denser, more efficient power conversion solutions from the grid to the core. 

Emerging power distribution architecture

Distribution of 415-480 VAC within data centers causes a patchwork of electrical conversions. AC power needs to be converted to DC power to support battery backup, and back to AC for further distribution.  But as AI systems scale up, this energy loss is too costly to absorb. A key focus area for the industry is high-voltage direct current (HVDC) distribution, which reduces conduction losses and the number of conversion stages in large clusters.

The main proposed solutions are either ±400 V (Mt. Diablo) or 800 V (Kyber) DC power delivery.  The first phase of HVDC solutions will still rely on 415-480 VAC distribution with a sidecar power rack, thereby reducing some power conversion losses.  This step has fewer power conversion stages than existing systems and reduces conduction losses by delivering HVDC to the adjacent compute rack.  However, to further eliminate power conversion stages, data centers will distribute HVDC throughout the cluster.  Additional energy savings will be achieved by implementing the 800V DC-DC conversion within the system trays in compute racks, reducing busbar conduction losses. This deployment will require a significant step up in density and efficiency. The past few months have seen hyperscalers specifying their general needs [2] of higher rack-power capacity, power efficiency, density, and scalability, as well as vendors responding with proposed converter topologies and considerations to meet those needs [3].  

This marks real progress, and it’s already clear that the key performance goals of the solutions are within reach. The benefits of these next-generation power delivery architectures include:

1. High conversion ratio – Conversion from HVDC distribution to very low XPU core voltage with as few stages as possible requires a large step-down ratio (>1000:1).  Solutions based on wide bandgap semiconductors such as gallium nitride (GaN) achieve higher conversion ratios due to higher breakdown voltages and reduced conduction and switching losses compared to silicon-based solutions.
2. Significant density increase compared to current power supply unit (PSU) designs – The increase in XPU power consumption does not come with a corresponding increase in available volume for power electronics. Computer and network architectures impose constraints on physical distance, necessitating more compact power components. Thanks to their excellent switching characteristics, GaN power semiconductors enable higher-frequency operation, allowing smaller energy-storage components such as capacitors, inductors, and transformers.
3. Extremely high efficiency at scale – The extraordinary growth in data center power consumption means that power losses in every stage translate directly to energy costs. Thus, the conversion ratio and high density must be achieved without sacrificing efficiency. GaN devices offer the best figures of merit—including lower specific on-resistance, minimal switching charge, and better high-frequency FOM—which result in the highest efficiency for a given ratio and density.

How GaN is driving data center innovation

The data center market demands not only advanced performance but also exceptional quality and reliability. Increasingly, industry consensus points to Power GaN as the key enabling technology for HVDC solutions in data centers. 

GlobalFoundries is developing GaN platforms to support this transition, including HV (650 V) and MV (200 V and below) devices. These platforms will offer industry-leading figures of merit (FoM) with the reliability and ruggedness that hyperscalers require to deploy AI at scale.

Opportunities for scaling HVDC architectures

Looking ahead to broad solution deployment, there are several major opportunities that remain, each offering room to drive the next wave of innovation on topology selection and device optimization:

• Establishing clear safety and isolation requirements: To date, safety and isolation have been discussed only in broad terms, but HVDC architectures will require isolation. Achieving safety and isolation compliance through spacing (creepage and clearance) can come at a high cost to density, while achieving compliance mechanically via conformal coating or potting can degrade thermal performance—both of which complicate serviceability of systems in the field. Defining the right balance represents a major opportunity for innovation in materials, mechanical structures, and system architecture.
• Defining EMI/EMC requirements for scaling next-generation data centers: With data centers subject to strict electromagnetic interference (EMI) and electromagnetic compatibility (EMC) standards, the industry must determine how topologies can meet them. If bulky filter components are required to scale HVDC solutions, this may prevent density targets from being met, potentially forcing alternate topology selection. It is crucial that these requirements scale to multi-GW data centers, allowing clusters to interoperate, otherwise compatibility and performance are at risk.
• Converging on optimal step-down ratios and system-level power conversion strategy: Will the industry converge to a 16x or 64x step-down, or, as the HVDC converter moves into the system tray, will system designers optimize the power conversion stages around different voltage levels?  If solutions are customized based on system-level optimization, this will likely lead to a need for regulated HVDC converters as well as unregulated fixed-ratio converters, with the two types having distinct transient requirements. These tradeoffs will affect overall system design in the future, from rack input to XPU.

Enabling scalable, efficient, and sustainable data centers

As these solutions evolve and mature, GF will collaborate with our customers to optimize device development, integrate driver and sensor functionality with power devices, and heterogeneously integrate power devices with additional components.  

It is encouraging that, along with the activity around converter feasibility, industry participants are also extremely active in pursuing open standards, such as the Open Compute Project’s Power Distribution sub-project, which will provide a roadmap for scalable, interoperable HVDC architectures. 

Adoption of HVDC architectures allows operators and OEMs to convert efficiency gains directly into XPU and network-cluster performance—delivering more usable floating-point operations per second (FLOPs) from the same energy footprint while reducing energy losses, lowering operational costs, improving rack-level density, and advancing sustainability goals through more efficient power delivery. Meeting these stringent demands at a massive scale requires solutions that ensure interoperability and long-term ecosystem value remain top priority.

Notes:

1. Future AI processors said to consume up to 15,360 watts of power — massive power draw will demand exotic immersion and embedded cooling tech | Tom’s Hardware
2. Asset Share – NVDAM 
3. Swing Aboard the 800-V Bus: NVIDIA’s AI Power Architecture and the Chips to Drive It | Electronic Design

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