Navitas tightens SiC losses with refined TAP

Navitas Semiconductor has announced its 5th-generation GeneSiC platform featuring high-voltage trench-assisted planar (TAP) SiC MOSFETs, describing it as a significant advancement over previous generations. The new 1200-V MOSFET line complements Navitas’ ultra-high-voltage 2.3-kV and 3.3-kV devices based on its 4th-generation GeneSiC technology.

The latest generation incorporates the company’s most compact TAP architecture to date, combining planar-gate ruggedness with trench-enabled performance gains to improve efficiency and long-term reliability. It targets high-voltage applications including AI data centers, grid and energy infrastructure, and industrial electrification.

Compared with the prior 1200-V devices, the new generation delivers a 35% improvement in R_DS(on) × Q_GD figure of merit, reducing switching losses and enabling cooler, higher-frequency operation. About a 25% improvement in Q_GD/Q_GS ratio, together with a stable high threshold voltage (V_GS,TH ≥ 3 V), strengthens switching robustness and improves immunity to parasitic turn-on in high-noise environments.

Navitas expects to introduce products based on its 5th-generation technology in the coming months. For additional information, contact a Navitas representative or email info@navitassemi.com.

Navitas Semiconductor

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