Materials unveiled for scaling copper wires at 2-nm and beyond

A new material claims to increase the performance-per-watt of chips by enabling copper wiring to scale to the 2-nm node and beyond while reducing resistance by as much as 25%. This new material with enhanced low-k dielectric material reduces chip capacitance and strengthens logic and DRAM chips for 3D stacking.

At this year’s SEMICON West, held from 9 to 11 July in San Francisco, California, Applied Materials unveiled the material engineering advances that extend copper chip wiring to the 2-nm node and below. But why are these material engineering efforts critical now?

As Applied Materials’ VP of technology, Dr. Mehul Naik, writes in his blog, if we don’t dramatically improve the efficiency of chips and systems, then the growth of artificial intelligence (AI) computing could be gated by the limits of the power grid. Below is a closer look at this premise.

The advances in patterning and subsequently continued lithographic scaling are making it possible to print ever-smaller transistor features on a chip. However, while chipmakers continue to shrink transistors with each generation, they must also shrink the trenches for the wiring. And, as chipmakers further scale the wiring, the barrier and liner take up a larger percentage of the volume intended for wiring.

As a result, it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space. That’s because while wires get thinner, electrical resistance increases. Moreover, as wires get closer together and the insulating dielectric material between the wires decreases, capacitance and electrical crosstalk increase, resulting in signal delays and distortion. The outcome of these wiring scaling issues is slower and more power-hungry chips.

Figure 1 To create wiring, engineers etch trenches into dielectric material and then line them with a thin stack of metals that typically includes a barrier layer to prevent copper from migrating into the chip, a liner to promote copper adhesion, and finally bulk copper that completes the signal wires. Source: Applied Materials

“While advances in patterning are driving continued device scaling, critical challenges remain in other areas, including interconnect wiring resistance, capacitance, and reliability,” said Sun-Jung Kim, VP and head of the Foundry Development Team at Samsung Electronics. He calls for materials engineering innovations to overcome these challenges.

So far, the semiconductor industry has addressed the performance-per-watt challenge through materials innovation in the smallest wires closest to the transistor layer. More than two decades ago, low-dielectric-constant or “low-k” dielectrics were introduced as the insulating materials between wires, replacing aluminum wiring with copper.

The combination of low-k dielectrics and copper became the semiconductor industry’s workhorse, continuously aided by exotic materials and materials engineering techniques. However, as the industry scales to 2 nm and below, thinner dielectric material renders chips mechanically weaker. Furthermore, narrowing the copper wires creates steep increases in electrical resistance that can reduce chip performance and increase power consumption.

That calls for new material solutions that enable the industry to scale low-resistance copper wiring to the emerging smaller nodes. “These low-k dielectric materials must reduce capacitance and strengthen chips to take 3D stacking to new heights,” said Dr. Prabu Raja, president of the Semiconductor Products Group at Applied Materials. “The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption.”

Applied Materials’ Black Diamond material surrounds copper wires with a k-value film engineered to reduce the buildup of electrical charges that increase power consumption and cause interference between electrical signals. Now, the Santa Clara, California-based company has unveiled an enhanced version of Black Diamond, which reduces the minimum k-value to enable scaling to 2 nm and below.

Figure 2 The Producer Black Diamond PECVD dielectric film enables chip scaling to 2 nm and below while offering increased mechanical strength for 3D logic and memory stacking. Source: Applied Materials

The enhanced version of Black Diamond also offers increased mechanical strength, which is critical as chipmakers and systems companies advance 3D logic and memory stacking. According to Applied Materials, several logic and DRAM chipmakers have adopted the new Black Diamond technology.

At SEMICON West 2024, Applied Materials also unveiled its Integrated Materials Solution (IMS), which combines six different technologies in one high-vacuum system. It includes a combination of materials that enables chipmakers to scale copper wiring to the 2-nm node and beyond.

It’s a binary metal combination of ruthenium and cobalt (RuCo), which simultaneously reduces the thickness of the liner by 33% at a 2-nm node. That, in turn, produces better surface properties for void-free copper reflow and reduces electrical line resistance by up to 25% to improve chip performance and power consumption.

Figure 3 The new binary metal combination of ruthenium and cobalt (RuCo) enables copper chip wiring to be scaled to the 2-nm node and beyond and reduces electrical line resistance by as much as 25%. Source: Applied Materials

While trade media is abuzz with advances in patterning and resulting lithographic scaling of chips, the smaller nodes will also lead to copper wiring hitting physical scaling limits. The materials engineering advances outlined in this blog are designed to increase the performance-per-watt of chips by enabling copper wiring to scale to the 2-nm node and beyond.

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