Lattice sets new standard for secure control FPGAs

Lattice Semiconductor claims the industry’s first post-quantum cryptography (PQC)-ready FPGAs with the launch of its MachXO5-NX TDQ family. Touted as the industry’s first secure control FPGAs, the MachXO5-NX TDQ family features full CNSA 2.0-compliant PQC support.

Built on the Lattice Nexus platform, these FPGAs target applications such as computing, communications, industrial, and automotive applications, addressing the continued threat of quantum-enabled cyberattacks.

The MachXO5-NX TDQ FPGA family provides the only complete CNSA 2.0 and National Institute of Standards and Technology (NIST)-approved PQC algorithms (LMS, XMSS, ML-DSA, ML-KEM, AES256-GCM, SHA2, SHA3, and SHAKE) offering robust protection against quantum threats, according to Lattice. Its authenticated and/or encrypted bitstream ensures data integrity and protection against unauthorized access with ML-DSA, LMS, XMSS, and AES256. It features crypto-agility via in-field algorithm update capability and anti-rollback version protection for ongoing alignment with evolving standards, and secure bitstream key management with revokable root keys and sophisticated key hierarchy for PQC and classical keys.

Advanced cryptography features include advanced symmetric and classical asymmetric cryptographic algorithms (AES-CBC/GCM 256 bit, ECDSA-384/521, SHA-384/512, and RSA 3072/4096 bit) for bitstream and user data protection. A device identifier composition engine, security protocol and data model, and Lattice SupplyGuard support provide attestation and secure lifecycle/supply chain management for future-proof, end-to-end security.

The FPGAs also provide hardware root of trust (RoT), delivering a trusted single-chip boot with integrated flash, a unique device secret that ensures distinct device identity, and integrated non-volatile configuration memory and user flash memory with flexible partitioning and secure locking. They also feature comprehensive locking control of the programming interface (SPI, JTAG), side channel attack resiliency, and NIST Cryptographic Algorithm Validation Program (CAVP) compliant algorithms.

In addition, Lattice expanded its RoT-enabled Lattice MachXO5-NX device family with new MachXO5-NX TD devices, offering new density and package options. The new Lattice MachXO5-NX TDQ and MachXO5-NX TD FPGA devices are currently available and are supported by the latest release of Lattice Radiant design software.

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