Hardware security to bolster interconnect IPs for SoCs, chiplets

Hardware security vulnerabilities have greatly expanded the attack surface beyond traditional software exploits, making hardware security assurance crucial in modern system-on-chip (SoC) designs. Chip interconnect specialist Arteris’ acquisition of semiconductor cybersecurity assurance supplier Cycuity is the latest reminder of how hardware security is becoming an inflection point in SoC design.

Arteris delivers data-movement IP hardware and IP block integration software to connect on-chip components and chiplets. On the other hand, Cycuity ensures the security of these semiconductor design building blocks and their interactions. Charles Janac, president and CEO of Arteris, claims that Cycuity’s technology and expertise will add to Arteris’ product portfolio, enabling chip designers to better understand and improve data movement security in chiplets and SoCs.

Figure 1 A security solution, built around a coverage metric tailored for hardware designs, enables chip designers to precisely measure the effectiveness of security protocols. Cycuity

Cycuity’s hardware security solutions prevent vulnerabilities throughout chip development—from IP blocks to RTL design to full systems—with systematic security assurance in software configuration via scalable, repeatable security verification. The San Jose, California-based firm specifies, integrates, and verifies security across a chip’s hardware development lifecycle.

Security is becoming critical to all types of chip designs because the attack potential has expanded to the hardware layer. As a result, silicon vulnerabilities can compromise electronic systems and expose unprotected information. The National Institute of Standards and Technology (NIST) has recently released data showing common vulnerabilities and exposures (CVEs) in hardware grew by more than 15 times over the last five years.

For Arteris’ network-on-chip (NoC) IPs, which provide the backbone for data movement across SoCs and chiplets, Cycuity’s offerings can help mitigate security vulnerabilities throughout the SoC hardware development cycle. They can uncover security weaknesses across firmware, IP blocks, chip subsystems, chiplets, and full SoCs.

Figure 2 This hardware security solution identifies secure design assets and ensures they are properly managed during secure boot. Source: Cycuity

Cycuity—which works closely with leading EDA toolmakers such as Cadence, Siemens EDA, and Synopsys—has its hardware security tools integrated with leading EDA environments. That allows chip designers to identify, verify, and resolve security risks before silicon implementation and production. For instance, they can safeguard against attacks exploiting microarchitectural side channels, logic bugs, third-party and open-source IP, unsecured interconnects, debug backdoors, and supply-chain gaps.

The acquisition deal, subject to regulatory approval, is expected to close in the first quarter of 2026.

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