CES 2025: Edge AI hardware acceleration highlights

Edge computing has been a hot topic, but what's underlying hardware and how do implementations vary? The post CES 2025: Edge AI hardware acceleration highlights appeared first on EDN.

CES 2025: Edge AI hardware acceleration highlights

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Edge computing has naturally been a hot topic at CES with companies highlighting a myriad of use cases where the pre-trained edge device runs inference locally to produce the desired output, never once interacting with the cloud. The complexity of these nodes has grown to not only include multimodal support with the fusion and collaboration between sensors for context-aware devices but also multiple cores to ratchet up the compute power.

Naturally, any hardware acceleration has become desirable with embedded engineers craving solutions that ease the design and development burden. The solutions vary where many veer toward developing applications with servers in the cloud that are then virtualized or containerized to run at the edge. Ultimately, there is no one-size-fits-all solution for any edge compute application.

It is clear that support for some kind of hardware acceleration has become paramount for success in breaking into the intelligent embedded edge. Company approaches to the problem run the full gamut from hardware accelerated MCUs with abundant software support and reference code, to an embedded NPU.

Table 1 highlights this with a list of a few companies and their hardware acceleration support.

Company

Hardware acceleration

Implemented in

Throughput

Software

NXP

eIQ Neutron NPU

select MCX, i.MX RT crossover MCUs, and i.MX applications processors

32 Ops/cycle to over 10,000 Ops/cycle

eIQ Toolkit, eIQ Time Series Studio

STMicroelectronics

Neural-ART Accelerator NPU

STM32N6

up to 600 GOPS

ST Edge AI Suite

Renesas

DRP-AI

RZ/V2MA, RZ/V2L, RZ/V2M

DRP-AI Translator,  DRP-AI TVM 

Silicon Labs

Matrix Vector Processor, AI/ML co-processor

BG24 and MG24

MVP Math Library API, partnership with Edge Impulse

TI

NPU

TMS320F28P55x, F29H85x, C2000 and more

Up to 1200 MOPS (on 4bWx8bD)

Up to 600 MOPS (on 8bWx8bD)

Model Composer GUI or Tiny ML Modelmaker

Synaptics

NPU

Astra (SL1640, SL1680)

1.6 to 7.9 TOPS

Open software with complete GitHub project

Infineon

Arm Ethos-U55 micro-NPU processor

PSOC Edge MCU series, E81, E83 and E84

ModusToolbox

Microchip

AI-accelerated MCU, MPU, DSC, or FPGA

8-, 16- and 32-bit MCUs, MPUs, dsPIC33 DSCs, and FPGAs

MPLAB Machine Learning Development Suite, VectorBlox Accelerator Software Development (for FPGAs)

Qualcomm

Hexagon NPU

Oryon CPU, Adreno GPU

45 TOPS

Qualcomm Hexagon SDK

Table 1: Various company’s approaches for hardware acceleration.

Synaptics, for instance, has its Astra platform that is beginning to incorporate Google’s multi-level intermediate representation (MLIR) framework. “The core itself is supposed to take in models and operate in a general-purpose sense,” said Vikram Gupta, senior VP and general manager of IoT processors at Synaptics. “It’s sort of like an open RISC-V core based system, but we’re adding an engine alongside it, so the compiler decides whether it goes to the engine or whether it works in a general-purpose sense.” 

“We made a conscious choice that we wanted to go with open frameworks. So, whether it’s a Pytorch model or a TFLite model, it doesn’t matter. You can compile it to the MLIR representation, and then from there go to the back end of the engine,” he added. One of their CES demos can be seen in Figure 1.

Figure 1:  A smart camera solution showing the Grinn SoM that uses the Astra SL1680 and software from Arcturus to provide both identification and tracking. New faces are assigned an ID and an associated confidence interval that will adjust according to the distance from the camera itself. 

At CES, TI showcased its TMS320F28P55x C2000 real-time controller (RTC) MCU series with an integrated NPU featuring an arc fault detection solution for solar inverter applications.

The system performs power conversion while at the same time doing real-time arc fault detection using artificial intelligence (AI). The solution follows the standard process of obtaining data, labeling, and training the arc fault models that are then deployed onto the C2000 device (Figure 2).

Figure 2: TI’s solar arc fault detection edge AI solution.

One of Microchip’s edge demos detected true touches in the presence of water using its mTouch algorithm in combination with their PIC16LF1559 MCU (Figure 3). Another solution highlighted was in partnership with Edge Impulse and used the FOMO machine learning (ML) architecture to perform object detection in a truck loading bay.

Figure 3: Microchip’s edge AI solutions at CES 2025 include truck loading bay augmented by AI in partnership with Edge Impulse (left) and a custom-tailored Microchip solution using their mTouch algorithm to differentiate between touch and water (right).

Other companies, such as Nordic Semiconductor, have also partnered with Edge Impulse to ease the process of labeling, training, and deploying AI to their hardware. The company has also eased the process of leveraging Nvidia TAO to adapt well-established AI models to a specific end-application on any Edge Impulse-supported target hardware.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

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The post CES 2025: Edge AI hardware acceleration highlights appeared first on EDN.

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