Putting 3D IC to work for you

3D IC chiplet-based heterogeneous package integration represents the next major evolution in semiconductor design. It allows us to continue scaling system performance despite the physical limitationA sneak peak at 3D IC design toolkits and workflowss of traditional monolithic chip manufacturing. By breaking functional systems into sub-functional chiplets and using advanced packaging integration technologies, we can create more complex, more powerful systems than ever before.

The challenge—and opportunity—for the industry is to lower the barriers to adoption of 3D IC design so that its benefits can become available industry-wide and not just the bleeding edge markets. Thus, the Chiplet Design Exchange (CDX) was formed within the Open Compute Project with the mission of developing easy-to-use, machine-readable design kits (3DKs).

With participation from EDA vendors, foundries, OSATs, and materials providers, the goal was to define standards and workflows for 3D IC design. In other words, a neutral, open foundation that enables efficient chiplet integration and reuse, accelerates innovation, and guarantees manufacturability across organizational boundaries.

3D IC design toolkits and workflows

Silicon IC design is supported by a mature ecosystem of IP libraries and standardized process design kits, but advanced packaging has historically lacked a similar infrastructure. 3D IC design requires new, specialized design kits tailored for chiplet-based workflows and advanced package integration complexity.

The CDX group, together with industry partners, defined four primary 3DK categories, each supporting a discrete aspect of 3D IC design, integration, and verification:

• Chiplet design kits (CDKs) provide standardized, reusable chiplet models with the necessary information for seamless system integration.
• Package assembly design kits (PADKs) define essential package rules such as I/O/TSV pitch, substrate and interposer spacing, and component placement guidelines to facilitate manufacturability.
• Material design kits (MDKs) contain composite material properties needed for accurate electrical and reliability simulations.
• Package test design kits (PTDKs) specify test I/O, pin dimensions, and functions, supporting robust automated testing at both the chiplet and system-in-package level.

Figure 1 A chiplet design kit (CDK) is shown as per the JEDEC JEP30 part model. Source: Siemens EDA

Standardizing these kits in machine-readable, EDA-neutral formats closes persistent gaps between silicon, packaging, and test communities. Every stakeholder—whether chiplet vendor, package architect, or manufacturing partner—can contribute, access, and leverage accurate models for design, verification, and production handoff to manufacturing.

The wider availability of 3DKs is driving the emergence of new, fluid 3D IC workflows. Chiplet suppliers can now publish detailed, standards-compliant digital models, creating a catalog of validated IP. Designers can search, evaluate, and select chiplets based on electrical, physical, and performance characteristics—similar to how SoC developers choose IP blocks for traditional integration. This enhances discoverability, accelerates design cycles, and fosters a new business model for silicon IP reuse.

Crucial to this flow is automation in model authoring. Manually crafting CDX-compliant 3DKs at scale is not practical, so the industry is investing in open-source, EDA-neutral authoring tools. Siemens EDA Innovator3D IC exemplifies this trend, providing a unified environment where teams can design, verify, and plan manufacturing in one cockpit. These platforms enable rapid iteration, simulation, and validation of heterogeneous integration, helping organizations reduce costly design spins and reach the market faster.

Figure 2 The Innovator3D IC Integrator facilitates a heterogeneous integration cockpit. Source: Siemens EDA

The AI and 3D IC alliance

Artificial intelligence (AI) and high-performance computing (HPC) are both driving, and benefiting from, progress in 3D IC technology. As scaling of traditional process nodes approaches its physical limits, chiplet integration and advanced packaging become the primary pathways to higher performance and capacity. By stacking high-bandwidth memory near logic, designers achieve higher data transfer rates with reduced latency and power—vital for AI, hyperscalers, and data-intensive applications.

The industry is also crossing new thresholds: single-die reticle limits are being surpassed, and panel-scale organic and glass interposers now support the assembly of thousands of chiplets—resulting in systems with trillions of transistors on a single substrate. The complexity of designing, laying out, and verifying these massive architectures is well beyond the reach of traditional manual processes, especially as electrical, power, thermal, and mechanical dependencies multiply.

AI is therefore becoming an indispensable partner, not just another tool. Machine learning accelerates fundamental EDA tasks, such as SPICE simulation, by orders of magnitude and powers multi-dimensional optimization engines that explore a vast design space automatically. Recent advances allow even legacy tools to achieve significant productivity gains by learning from the design intent and usage patterns, automating and refining iterative processes to deliver greater productivity and better results.

Figure 3 AI is both creating new challenges for semiconductor design and providing solutions to those same challenges. Source: Siemens EDA

One emerging area is the use of AI-driven optimization for physical design, layout, and verification of large-scale 3D assemblies. By encoding design rules, material properties, and system constraints as machine-readable data—rather than static PDF documents—organizations can automate decision-making, error-checking, and design-space exploration.

In the future, a hierarchy of AI agents will actively collaborate, each addressing a specialized workflow (for example, thermal analysis, high-level partitioning, or chiplet floorplanning) and communicate and negotiate based on user guidance and systemic feedback, vastly reducing cycle times and mitigating design risk.

As the industry begins to explore the use of co-packaged optics (CPO) and photonic integration—addressing I/O bottlenecks in massive 3D IC systems—AI’s role will become even more critical, both in design and in real-time adaptation and optimization for manufacturing and field operation.

The next major semiconductor evolution is here

The semiconductor industry’s progression from painstaking, manual layout at the 5-micron node to today’s nanometer-scale devices with trillions of transistors is extraordinary. 3D ICs mark the next great leap, promising new levels of performance, system complexity, and integration—even as Moore’s Law slows.

This evolution demands not just technical advances but organizational transformation. The shift from product-centric thinking to system-level solutions, the rise of cross-disciplinary workflows, and the expanding role of AI and automation are now prerequisites as 3D IC moves from early adoption to mainstream practice.

Open 3D standards, robust tooling, and EDA-neutral platforms, together with the enablement of AI-augmented flows are laying the foundation for a future where advanced packaging unleashes the full potential of modern electronics.

As we move into the trillion plus-transistor era, innovations in 3D IC design and the power of AI will define what is possible in electronic system design—and ensure that future engineers and systems remain at the leading edge of technology and capability.

Todd Burkholder is a senior editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Tony Mastroianni is the Advanced Packaging Solutions Director at Siemens Digital Industries Software. He has more than 30 years’ experience as an engineer and engineering manager in the global semiconductor industry and currently leads development of advanced packaging solutions for Siemens EDA. Prior to joining Siemens, he served in engineering leadership positions at Inphi and eSilicon. Tony earned a B.S.E.E from Lehigh University and a M.E.E at Rutgers University.

Editor’s Note

This is the second part of the three-part article series about 3D IC architecture. The first part, published last week, provided essential context and practical depth for design engineers working on 3D IC systems. The third and final part, to be published next week, will provide a comprehensive framework for 3D IC integration.

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