EDA tools enable PCIe, UCIe simulation

System Designer for PCIe from Keysight enhances design productivity by supporting simulation workflows compatible with industry standards. The design environment, which is part of the Advanced Design System (ADS) suite, allows engineers to model and simulate PCIe Gen5 and Gen6 systems. Additionally, Keysight has added new features to its Chiplet PHY Designer, a simulation tool that complies with UCIe standards.

System Designer for PCIe automates the setup for multilink, multilane, and multilevel (PAM4) PCIe systems. The design environment also includes the PCIe AMI Model Builder, enabling the creation of models for both transmitters and receivers, and supporting NRZ and PAM4 modulations. A streamlined workflow with simulation-driven virtual compliance testing ensures design quality and reduces design iterations.

Chiplet PHY Designer for UCIe estimates chiplet die-to-die link margin, measures voltage transfer function (VTF) for channel compliance, and analyzes forward clocking. New design exploration and report generation features accelerate signal integrity analysis and compliance verification.

For more information, apply for a free trial, or obtain a price quote, follow the product page links below.

System Designer for PCIe

Chiplet PHY Designer 

Keysight Technologies 

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