Crypto mining SoC unearths a need for custom IP

Here is how the impact of custom cells can ripple through the SoC design flow, from tape-out and beyond. The post Crypto mining SoC unearths a need for custom IP appeared first on EDN.

Electronics Jul 14, 2026 0 5 Add to Reading List

Crypto mining SoC unearths a need for custom IP

Conflicting application requirements can turn system-on-chip (SoC) design into a hall of mirrors. In particular, choosing a process technology can become a maze of contradictions and puzzles.

Then there is higher speed, which generally requires more power. Next, the technology that delivers the necessary performance and power efficiency may be unacceptable due to cost or supply-chain constraints.

However, a design partner who can customize foundational IP—logic cell libraries or memories—and shepherd the custom cells through the design flow, manufacturing, and testing can often bring an SoC design safely through the maze.

One recent engagement with a crypto-mining client illustrates the importance of custom foundational IP in resolving these trade-offs. And it also shows how the impact of custom cells can ripple through the design flow, from tape-out and beyond, emphasizing the need for a design partner with expertise in both IP creation and SoC implementation.

A unique application

Crypto mining is the process of generating new coins in a cryptocurrency. For many such currencies, including the ubiquitous Bitcoin, the process requires a so-called proof-of-effort: a computationally intensive task with no known shortcut.

Factoring a huge number is an example: the only way to find the prime factors is to keep trying new prime numbers. In principle, the cryptocurrency’s governors would publish a large number, the crypto miners would set to work searching for factors, and the first miner to publish all the factors would receive a new coin.

Obviously—luck aside—the miners with the most computing power will get the most coins. That leads to a computing arms race. Less obviously, this game consumes a tremendous amount of energy—one reason China attempted to ban crypto mining in 2021. To make the enterprise profitable, the miners need to stay on the leading edge of computing performance while minimizing capital investment and operating costs. These costs are dominated by power consumption.

Under those pressures, crypto miners quickly migrated from farms of CPU-based server boards to FPGAs, and then to vast arrays of ASIC hardware. Today, miners demand high computing performance, very low power consumption, very low front-end investment, and low unit cost—a set of contradictory requirements.

The mining SoC

This was the scenario presented to us by our crypto-mining client. Together, we determined that the lowest-cost approach that met their performance and power requirements would be a FinFET process with an extremely low operating voltage.

In fact, we had fully characterized 0.5-V logic libraries for this process. There was just one problem. The library could not meet the client’s speed requirements. The problem, it turned out, was the registers. This library, like virtually all standard logic libraries, uses a conventional master-slave D-type flip-flop. But it could not operate reliably at the required clock frequency. So, we decided to create a custom D-type flip-flop cell.

The D flip-flop

The D-type flip-flop has been a fundamental element in digital design for decades, used for everything from state machines to registers (Figure 1).

Figure 1 Schematic highlights a 32-bit D-flip-flop used to implement D-type registers. Source: Faraday Technology

The cell’s performance and stability are vital to any RTL design. The conventional cell design uses two stages and two clock phases. The first stage captures the input data on one clock edge, and the second stage latches the captured data on the second clock edge. In most designs, this requires routing two very accurately timed clock phases to every flip-flop cell.

We believed we could eliminate one of these clock signals and achieve a higher operating speed. Eliminating one clock would also substantially reduce the cell’s power dissipation and could reduce area and routing congestion.

But could we accomplish this, and hit the required frequency? And could we do all that while sacrificing the inherent stability of the dual-phase clock approach and still have a device that is resistant to process variations and electrical upset?

The TSPC flip-flop

Our exploration of circuit designs led to the development of the true single-phase clock (TSPC) D-type flip-flop (Figure 2).

Figure 2 Schematic of a traditional positive-edge triggered TSPC flip-flop showing how a TSPC flip-flop would meet the customer’s power requirements. Our proposed circuit design allowed the TSPC flip-flop to also operate over the necessary frequency range. Source: Faraday Technology

However, circuit design and proof of concept were just the beginning. We fully simulated the circuit in SPICE to understand the layout and sensitivities of this novel cell. We needed to characterize the TSPC flip-flop not only in isolation but also in a dense layout surrounded by other cells, under marginal, noisy clocks, and process variations. At last, we reached our goals for both performance and reliability.

The SoC design using our TSPC flip-flop met our crypto-mining client’s speed requirements. The cell also achieved a 40% reduction in power at rated speed compared to the conventional D-type flip-flop cell it replaced. It reduced the area by about 7%. And from a functional perspective, the TSPC cell was simply a normal D-type flip-flop.

But our detailed characterization of the cell revealed differences in the new device’s operating characteristics. These differences would influence the implementation flow for the SoC.

The cell in use

One unique characteristic of the TSPC cell influences front-end design, specifically power management planning. The single-phase clock for the TSPC flip-flop must not stop during operation, or the flip-flop state may be lost. This places significant limits on the use of power-management techniques such as clock gating and clock throttling. A design that interrupts the register clock must tolerate an unpredictable state when the clock resumes.

Other special characteristics of the cell further influence downstream design. For example, the cell is quite sensitive to clock signal integrity. This requires careful, skilled planning of clock networks from the outset and equally careful routing of clock trees. Conventional clock-tree synthesis tools may not deliver the necessary signal quality across all flip-flop instances, resulting in unreliable operation.

The cell is also sensitive to process variations, even at a local level. This issue can impact yield, but it can be overcome by careful placement during logic layout. We generally use manual insertion to instantiate the TSPC cells, as we have found them unsuitable for use with synthesis tools. Once the cells are placed, routing constraints are relatively minimal. The foremost issue is to maintain signal integrity on the clock lines.

Timing analysis is straightforward, of course, using the TSPC cell’s timing data. Signoff is also conventional—with the enhanced attention to clock integrity. Thanks to our exhaustive characterization and refinement of the cell design, there are no special process corners to be investigated. During test, some changes to the test vectors may be helpful to inspect the unique behavior of the cells.

A new degree of freedom

SoC designers are used to trading off power, speed, and process to meet design requirements. But sometimes no setting of these knobs will achieve the desired result. Our crypto-mining client faced this challenge: running an affordable, available FinFET process at 0.5 V would achieve all design goals except maximum speed. But consuming more power or moving to a more advanced process node in exchange for more speed was not an acceptable trade-off.

The solution was to move outside the power-performance process box with customized foundational logic. Faraday determined that we could meet the client’s needs with only one custom cell—a novel D-type flip-flop design. But once characterized, we found that the cell would place significant demands on the implementation team, from power planning through test design (Figure 3).

Figure 3 To reduce power consumption, we used a TSPC circuit to replace a master-slave flip-flop; but TSPC has an operating frequency limit, so we proposed a solution to this limitation. Source: Faraday Technology

The TSPC flip-flop thus could have become only academic exercise. However, it became an out of the box solution here. Today, the crypto-mining SoC is in volume production and meets all design requirements. The chips are out there, searching for coins and earning their living.

Jason Kang is director of IP technology at Faraday Technology. He has over 20 years of experience in fundamental IP development, PDK integration, and IP model characterization. His expertise lies at the intersection of advanced-node design flows, device modeling, and EDA methodologies, with a strategic focus on silicon implementation and the emerging field of AI-driven design automation.