Alphawave Semi’s quest for open chiplet ecosystem

The open chiplet ecosystem is steadily taking shape, one design demonstration at a time. Take, for instance, Alphawave Semi, which has announced the tape-out of what it claims to be the industry’s first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC’s 7-nm process node.

This multi-standard I/O chiplet employs an IP portfolio complaint with Ethernet, PCIe, CXL, and Universal Chiplet Interconnect Express (UCIe) Revision 1.1 standards. It delivers a total bandwidth of up to 1.6 Tbps with up to 16 lanes of multi-standard PHY supporting silicon-proven PCIe 6.0, CXL 3.x, and 800G Ethernet IPs.

Figure 1 The tape-out of the off-the-shelf, multi-protocol I/O connectivity chiplet demonstrates the integration of advanced interfaces. Source: Alphawave Semi

A couple of months ago, Alphawave Semi announced the development of a chiplet connectivity platform on TSMC’s 3-nm process node. It’s a UCIe subsystem comprising PHY and controller which can deliver 24 Gbps data rates. The 24-Gbps UCIe subsystem is compliant with the UCIe Revision 1.1 specification and includes a highly configurable die-to-die controller that supports streaming, PCIe/CXLTM, AXI-4, AXI-S, CXS, and CHI protocols.

Figure 2 The UCIe subsystem features bit error rate (BER) health monitoring to ensure reliable operation. Source: Alphawave Semi

Alphawave Semi demonstrated the above two designs at the Chiplet Summit 2024 in Santa Clara, California, earlier this year.

In its quest to pave the way for open chiplet ecosystems, Alphawave Semi has also joined hands with Arm on the compute side. It has recently announced the development of a compute chiplet built on Arm Neoverse Compute Subsystems (CSS) for artificial intelligence (AI) and machine learning (ML), high-performance compute (HPC), data center, and 5G/6G networking infrastructure applications.

Such a collaboration brings a chiplet connectivity specialist like Alphawave Semi a portfolio that includes IO extension chiplets, memory chiplets, and compute chiplets. Combining Arm’s compute building blocks with Alphawave Semi’s connectivity IP will also bolster the creation of an open chiplet ecosystem.

Figure 3 The compute chiplet combines the Arm Neoverse CSS platform with Alphawave Semi’s connectivity IPs for UCIe, 112/224G Ethernet, and HBM subsystems. Source: Alphawave Semi

The chiplet design examples outlined above mark a clear trend: the developments of key chiplet building blocks are steadily taking shape, also bolstering its multi-protocol ecosystem. With the maturation of chiplet standards like UCIe and the availability of silicon-proven chiplet subsystems, design engineers can reduce development time, lower costs, and create greater synergy with their existing hardware ecosystems.

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