Thermal analysis tool aims to reinvigorate 3D-IC design

The mainstream adoption of 3D-IC has become a question mark due to critical challenges ranging from early-stage chip designs to 3D assembly exploration to final design signoff. A new EDA tool claims to address these issues by integrating thermal analysis directly into all stages of the IC design flow, spanning early analysis to signoff analysis, while offering multiple-use models.

At this year’s Design Automation Conference (DAC) in San Francisco, California, Siemens EDA unveiled Calibre 3DThermal software for thermal analysis, verification, and debugging in 3D integrated circuits (3D-ICs). It enables chip designers to rapidly model, visualize, and mitigate thermal effects in their designs from early-stage chip design to package-inward exploration to design signoff.

Figure 1 Calibre 3DThermal is a thermal analysis solution based on a complete understanding of the 3D-IC assembly. Source: Siemens EDA

In all design flows, Calibre 3DThermal captures and analyzes thermal data across the entire design lifecycle. Siemens EDA has already joined forces with UMC to deploy a thermal analysis flow based on Calibre 3DThermal.

What’s hampering 3D ICs

Semiconductor engineering teams focusing on designing and manufacturing bleeding edge, next-generation chips are turning to chiplets and 3D-IC architectures to integrate more functionality into ever-shrinking footprints. However, despite lots of talk, commercially available semiconductors based on 3D-IC architectures are still quite hard to find in the marketplace.

Why? 3DIC architectures—which place multiple dies or chiplets next to one another or even stack dies vertically in a single package—present a range of new complexities and challenges due to higher numbers of active dies in close proximity to each other or stacked vertically.

In other words, squeezing multiple active dies in such close proximity—side-by-side or stacked vertically—in a single package comes with a host of new and vexing challenges. These challenges—sometimes categorized as multi-physics—often relate to controlling heat dissipation since excessive heat can impact the end device’s performance and reliability.

“There has been a view that 3D IC is going to take over the world, but no one is going to abandon Moore’s Law transistor scaling,” said Michael White, senior director of physical verification product management for Calibre design solutions at Siemens EDA. “However, 3D IC will be used for heterogeneous solutions in compute-intensive artificial intelligence (AI) chips.”

At advanced nodes like 2-nm, 3D IC makes sense, he added. “Whether it’s application processor, CPU or GPU, parts like I/O and HBM are going to be separate dies or separate chiplets, and it’s all going to be packaged in 2.5D or 3D IC.” However, in these advanced packages, controlling heat dissipation becomes imperative.

Moreover, design engineers can’t afford to wait until the assembly is complete to identify and correct errors; it can severely disrupt design schedules.

“There is a lot of heat to be managed,” White said. “Otherwise, it can impact transistor behavior in this new multi-physics domain.” He also added that thermal impacts could couple with stress impacts coming from new materials, how we stack, and placing of through silicon vias (TSVs) close to active transistors.

Thermal analysis to rescue

White makes the case for a shift-left approach with Calibre physical verification to help designers do things right the first time instead of close to tape-out. While talking to EDN before the launch of Calibre3DThermal, he pointed to its key feature, feasibility analysis, which allows chip designers to start the initial analysis with minimal inputs. “Once more information is available, it continuously refines the accuracy of the analysis.”

Figure 2 The shift-left approach enables chip designers to identify and resolve issues early in design flow with signoff-quality solutions. Source: Siemens EDA

John Ferguson, senior director of DRC/3DIC product management for Calibre design solutions, pointed out that chip designers spend years developing complex 3D ICs, and after a thermal signoff, if they find a problem, there is nothing they can do about it. “The idea of feasibility analysis is to start finding potential problems early.”

Chip designers can later perform more detailed analyses considering metalization details and their impact on thermal considerations as more detailed information becomes available. This progressive approach enables designers to refine their analysis, apply fixes like floorplanning changes, and add stacked vias or TSVs to avoid thermal hotspots and dissipate heat more effectively.

The iterative process continues until the final assembly is complete. Ferguson is quick to note that Calibre3DThermal is a bit different than traditional thermal analysis. “We have a faster way of performing thermal analysis in which the Calibre part will work upfront to look at the die level information, create accurate models, and pass that for creating models at the package level.”

Calibre with multi-use models

Calibre 3DThermal—developed to address the challenges of 3D-IC architectures where controlling heat dissipation is a key requirement—offers fast and accurate approaches to identifying and rapidly addressing complex thermal issues. It allows designers to iterate thermal analysis at whichever design stage they are working on.

Thermal analysis at this advanced level requires a complete understanding of the 3D-IC assembly, so Calibre 3DThermal embeds a custom version of Siemens’ Simcenter Flotherm software solver engine to create precise chiplet-level thermal models for static or dynamic simulation of full 3D-IC assemblies. Next, debugging is streamlined through the traditional Calibre RVE software results viewer.

It’s worth noting that even when you put a known good die (KGD) into a package, you might get heat issues.

“Once you have more dies, you can perform more mature thermal analysis at a much more fine-grained level,” Ferguson said. “When you bring all dies into the package, that’s when you add extra accuracy and then look at selective chiplets or selective IPs in those chiplets.”

Now that chip designers have information at the dies and package levels, this information can be passed upstream to the board level or even to the large system level, like a jet engine design.

Related Content

• A thermal-aware IC design methodology
• The Importance of 3D IC Ecosystem Collaboration
• Reliability challenges in 3D IC semiconductor design
• How the Worlds of Chiplets and Packaging Intertwine
• Heterogeneous Integration and the Evolution of IC Packaging

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