NoCs and the transition to multi-die systems using chiplets

Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs) and systems-on-chip (SoCs). Traditionally favored for simplicity and cost-effectiveness, these single-die systems have driven the semiconductor industry’s advancements for decades.

However, as the demand for more powerful and versatile technology grows, the limitations of monolithic dies, particularly in terms of scalability and yield, become increasingly significant. This challenge has prompted a shift toward multi-die systems using chiplets.

Emerging trends in multi-die systems

The semiconductor industry is shifting toward multi-die architectures using chiplets to enable more flexible, scalable, and efficient designs. This transition involves a change in physical architecture and collaborative innovation among various ecosystem players to integrate diverse technologies into a single system.

Chiplets offer a modular approach to design, distributing different functionalities across multiple dies, which enhances yield and functional diversity. This method facilitates the integration of heterogeneous chiplets—such as digital logic implemented on a cutting-edge 5-nm process, with analog-to-digital converters (ADCs) and RF modules on larger, more cost-effective 16-nm and 28-nm processes.

Such configurations optimize power and cost efficiency and significantly improve the overall system performance by tailoring each die to specific operational needs. The trend toward assembling homogeneous chiplets into unified processors or accelerators further exemplifies this innovation, highlighting the versatility and scalability of multi-die systems.

To date, only a few industry giants like AMD, Intel and Nvidia have been using chiplet technologies, maintaining total control over every aspect of the development flow. However, smaller companies are also entering the field, contributing to a trend toward a more collaborative model where designers can mix and match chiplets from multiple vendors. This shift fosters innovation and encourages standardization among chiplet interfaces, crucial for compatibility and interoperability across different technologies and platforms.

Making this future a reality requires an ecosystem of partners, each playing a distinct role. To develop multi-die systems with optimized architectures, access to a variety of chiplets is essential. Many of these will be supplied by trusted third-party vendors, while others will be developed in-house to meet specific design requirements.

Some designers will focus on developing the chiplets themselves, while others will specialize in the technologies that connect the chiplets together. Additionally, teams will create the tools required to analyze and optimize the functionality and performance of the entire multi-die system.

NoC technology in chiplet integration

As the collaborative approach offered by chiplets becomes more prevalent, the technical challenges of integrating these diverse components become more apparent. Effective communication between chiplets is essential for ensuring that multi-die systems function smoothly. To address these integration challenges, network-on-chip (NoC) technology is becoming increasingly relevant.

NoCs have been the predominant way to connect IP blocks on monolithic SoCs. This interconnect IP can span the entire chip, facilitating the integration of various IP functions such as processors, accelerators, controllers, peripherals, and various interfaces to the outside world. While we will focus on a limited set of IP functions for this discussion, it’s important to note that a real device may be composed of hundreds of large, complex IPs.

Choosing the right NoC configuration is crucial for chiplet-based designs, as it significantly impacts the system’s communication, performance, scalability, and energy efficiency. Depending on their application needs and workload requirements, developers can select from a range of NoC topologies like star, ring, mesh and others, as shown in Figure 1.

Figure 1 These diagrams are examples of NoC topologies. Source: Arteris

It’s becoming increasingly common to have multiple NoCs on the same SoC; for example, a mesh linking an array of homogeneous accelerator IPs, a tree linking the other IPs, and a bridge between them. In fact, 10 or more NoCs on one SoC is not uncommon.

As we move into the chiplet age, complementing their penetration into IPs, NoCs will also be used to integrate the chiplets on the multi-die system substrate. If we consider only a star topology for simplicity, we see a hierarchical structure, as illustrated in Figure 2.

Figure 2 The above diagram illustrates a hierarchy of star-topology NoCs. Source: Arteris

Multi-die system integration automation

With a variety of NoC topologies available to enhance chiplet communication, the focus shifts to optimizing the design and testing processes. This is achieved through the “shift-left” concept, which was originally conceived as an approach to software and system testing.

The idea is to perform testing earlier in the lifecycle, moving left on the project timeline. The shift-left philosophy has been adopted by many disciplines, including architectural exploration, functional verification, and performance optimization by SoC developers.

Also required is a shift-left with respect to tasks like verifying the design via software simulation and hardware emulation. This requires a high degree of automation, including the ability to generate SystemC models of the IPs and NoCs, manage hundreds of thousands of control and status registers (CSRs), integrate everything together using IP-XACT-based tools, and perform simulation/emulation and performance analysis. Implementing the shift-left concept effectively demands collaboration across the industry.

Many companies are already looking at providing general-purpose chiplets, such as Arm and RISC-V processor clusters, memories, and transceivers. Companies are also collaborating on industry standards and protocols like Universal Chiplet Interconnect Express (UCIe), an open specification for a die-to-die interconnect between chiplets.

IP vendors like Arteris provide coherent and non-coherent NoC interconnect IP, including the ability to generate SystemC models of the configured IP for use in simulation and emulation. Next, EDA vendors are providing tools for simulation, emulation and performance analysis, such as Synopsys with its Platform Architect.

The evolution from monolithic dies to multi-die systems using chiplets marks a pivotal advancement in semiconductor technology. It truly takes an ecosystem of partners to develop and refine multi-die systems effectively. This collaborative environment will bring together diverse industry players, from chiplet manufacturers to software developers, each contributing to overcoming integration complexities.

Together, these efforts set the stage for the next generation of scalable, efficient and high-performance ICs, paving the way for innovative technological advancements and future market demands.

Ashley Stevens, director of product management and marketing at Arteris, has over 35 years of industry experience and previously held roles at Arm, SiFive and Acorn Computers.

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